Naresh Beguru Kasinath
I am an Engineer responsible to improve the layout quality at Intel. My domain expertise is Design for... | San Jose, California, United States
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Naresh Beguru Kasinath’s Emails na****@in****.com
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Naresh Beguru Kasinath’s Location San Jose, California, United States
Naresh Beguru Kasinath’s Expertise I am an Engineer responsible to improve the layout quality at Intel. My domain expertise is Design for Manufacturability (DFM) or FILL. Summary • Strong fundamentals in VLSI. • Working knowledge of Intel process nodes and design rules. • Hands-on experience in Layout Completion to meet density and improve yield. Interests • Digital Circuit Design, Physical Design, Process Architecture, Low Power Design Methodologies. Values • Integrity • Enthusiasm • Teamwork
Naresh Beguru Kasinath’s Current Industry Intel
Naresh
Beguru Kasinath’s Prior Industry
Arizona State University
|
Intel
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Work Experience
Intel
Lead DFM Engineer
Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Component Design Engineer
Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Arizona State University
Field-Programmable Gate Arrays Engineer
Wed Jan 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Arizona State University
Graduate student,
Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Naresh Beguru Kasinath Email Addresses
FAQ About Naresh Beguru Kasinath
-
Naresh Beguru Kasinath is located at
San Jose, California, United States -
Naresh Beguru Kasinath is a
I am an Engineer responsible to improve the layout quality at Intel. My domain expertise is Design for Manufacturability (DFM) or FILL. Summary • Strong fundamentals in VLSI. • Working knowledge of Intel process nodes and design rules. • Hands-on experience in Layout Completion to meet density and improve yield. Interests • Digital Circuit Design, Physical Design, Process Architecture, Low Power Design Methodologies. Values • Integrity • Enthusiasm • Teamwork Intel -
Naresh Beguru Kasinath currently works in the
Intel -
Naresh Beguru Kasinath specializes in
I am an Engineer responsible to improve the layout quality at Intel. My domain expertise is Design for Manufacturability (DFM) or FILL. Summary • Strong fundamentals in VLSI. • Working knowledge of Intel process nodes and design rules. • Hands-on experience in Layout Completion to meet density and improve yield. Interests • Digital Circuit Design, Physical Design, Process Architecture, Low Power Design Methodologies. Values • Integrity • Enthusiasm • Teamwork -
Naresh Beguru Kasinath speaks the following languages:
No languages available. -
Naresh Beguru Kasinath has prior experience in the following industries:
Intel , Arizona State University , Arizona State University -
Naresh Beguru Kasinath has the following professional experience:
Intel , Intel , Arizona State University , Arizona State University . -
You can view Naresh Beguru Kasinath’s
LinkedIn profile at LinkedIn URL. -
Naresh Beguru Kasinath’s work email addresses are
[email protected]. -
Naresh Beguru Kasinath works at
Intel
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